1. Field of the Invention
The present invention generally relates to a reconfigurable bus architecture, and more specifically, relates to a reconfigurable bus architecture for a battery application.
2. Description of the Related Art
In battery management, it is necessary to monitor the status of a battery, such as each cell voltage, pack voltage and each cell environment temperature, by Analog Front End (AFE) devices or analog to digital converter. The analog front end device is coupled to the battery. The digital data will be transferred to a microprocessor for various purposes, such as OCV (Open Circuit Voltage), cell impedance tracking, SOC (State of Charge), SOH (State of Health), cell balance, coulomb counting or protection purpose due to OV (Over Voltage)/UV (Under Voltage), OT (Over Temperature)/UT (Under Temperature), or OC (Over Current)/SC (Short Circuit).
With increasing the number of the cells of the stacked battery, the voltage of the stacked battery will become higher and higher. Further, the voltage capacity of an analog front end device is limited by the pin count of the AFE device or the physical process breakdown voltage of the AFE device. In this case, only one analog front end device is not enough to monitor the whole stacked battery. A plurality of analog front end devices is needed to monitor the status of the stacked battery. As consequence, the operation of these analog front end devices and their interaction with the stacked battery become more complex. These devices communicate with each other through several different buses and efficient management of these devices becomes an issue for stack battery efficiency.
Therefore, there is a need for a flexible bus architecture that can be used in a stacked battery that enables efficient management of the analog front end devices.